Compiling for Vector-thread Architectures

TitleCompiling for Vector-thread Architectures
Publication TypeConference Paper
Year of Publication2008
AuthorsHampton, M., & Asanović K.
Conference NameInternational Symposium on Code Generation and Optimization (CGO
Date Published04/2008
Conference LocationBoston, Massachusetts

Vector-thread (VT) architectures exploit multiple forms of parallelism simultaneously. This paper describes a compiler for the Scale VT architecture, which takes advantage of the VT features. We focus on compiling loops, and show how the compiler can transform code that poses difficulties for traditional vector or VLIW processors, such as loops with internal control flow or cross-iteration dependences, while still taking advantage of features not supported by multi-threaded designs, such as vector memory instructions. We evaluate the compiler using several embedded benchmarks and show that we can obtain substantial speedups over a
single-issue, in-order scalar machine.

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