Optimization of Sparse-Matrix-Vector Multiplication on Emerging Multicore Platform

TitleOptimization of Sparse-Matrix-Vector Multiplication on Emerging Multicore Platform
Publication TypeJournal Article
Year of Publication2007
AuthorsWilliams, S., Oliker L., Vuduc R., Shalf J., Yelick K. A., & Demmel J.
JournalParallel Computing- Special Issue on Revolutionary Hardware
ISBN Number978-1-59593-764-3
Abstract

We are witnessing a dramatic change in computer architecture due to the multicore paradigm shift, as every electronic device from cell phones to supercomputers confronts parallelism of unprecedented scale. To fully unleash the potential of these systems, the HPC community must develop multicore specific optimization methodologies for important scientific computations. In this work, we examine sparse matrix-vector multiply (SpMV) - one of the most heavily used kernels in scientific computing - across a broad spectrum of multicore designs. Our experimental platform includes the homogeneous AMD dual-core and Intel quad-core designs, the heterogeneous STI Cell, as well as the first scientific study of the highly multithreaded Sun Niagara2. We present several optimization strategies especially effective for the multicore environment, and demonstrate significant performance improvements compared to existing state-of-the-art serial and parallel SpMV implementations. Additionally, we present key insights into the architectural tradeoffs of leading multicore design strategies, in the context of demanding memory-bound numerical algorithms.

DOI10.1145/1362622.1362674
AttachmentSize
Matrix-Vector - RH '07973.07 KB