Silicon-Photonic Clos Networks for Global On-Chip Communication

TitleSilicon-Photonic Clos Networks for Global On-Chip Communication
Publication TypeConference Paper
Year of Publication2009
AuthorsJoshi, P., Batten C., Kwon Y. - J., Beamer S., Shamim I., Asanović K., & Stojanovic V.
Conference Name3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS) 2009
Date Published05/2009
Conference LocationSan Diego, CA

Future manycore processors will require energy-efficient, high-throughput on-chip networks. Silicon-photonics is a promising new interconnect technology which offers lower power, higher bandwidth density, and shorter latencies than electrical interconnects. In this paper we explore using photonics to implement low-diameter non-blocking crossbar and Clos networks. We use analytical modeling to show that a 64-tile photonic Clos network consumes significantly less optical power, thermal tuning power, and area compared to global photonic crossbars over a range of photonic device parameters. Compared to various electrical on-chip networks, our simulation results indicate that a photonic Clos network can provide more uniform latency and throughput across a range of traffic patterns while consuming less power. These properties will help simplify parallel programming by allowing the programmer to ignore network topology during optimization.

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