A Case for FAME: FPGA Architecture Model Execution

TitleA Case for FAME: FPGA Architecture Model Execution
Publication TypeConference Paper
Year of Publication2010
AuthorsTan, Z., Waterman A., Cook H. M., Bird S., Asanović K., & Patterson D.
Conference NameInternational Symposium on Computer Architecture (ISCA-2010)
Date Published06/2010
Conference LocationSaint-Malo, France

Given the multicore microprocessor revolution, we argue that the architecture research community needs a dramatic increase in simulation capacity. We believe FPGA Architecture Model Execution (FAME) simulators can increase the number of useful architecture research experiments per day by two orders of magnitude over Software Architecture Model Execution (SAME) simulators. To clear up misconceptions about FPGA-based simulation methodologies, we propose a FAME taxonomy to distinguish the cost-performance
of variations on these ideas. We demonstrate our simulation speedup claim with a case study wherein we employ a prototype FAME simulator, Midas, to research the interaction between hardware partitioning mechanisms and operating system scheduling policy. The study demonstrates the FAME capabilities: we run a modern parallel benchmark suite on a research operating system, simulate 64-core target architectures with multi-level memory hierarchy timing models, and add experimental hardware mechanisms to the target
machine. The simulation speedup achieved by our adoption of FAME—250 ×–allows longer experiments that reach different conclusions than those from shorter experiments necessitated by SAME.

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