Automatic Generation of Application-Specific Accelerators for FPGAs from Python Loop Nests

TitleAutomatic Generation of Application-Specific Accelerators for FPGAs from Python Loop Nests
Publication TypeConference Paper
Year of Publication2012
AuthorsSheffield, D., Anderson M., & Keutzer K.
Conference NameField Programmable Logic (FPL) 2012
Abstract

We present Three Fingered Jack, a highly productive approach
to mapping vectorizable applications to the FPGA.
Our system applies traditional dependence analysis and reordering
transformations to a restricted set of Python loop
nests. It does this to uncover parallelism and divide computation
between multiple parallel processing elements (PEs)
that are automatically generated through high-level synthesis
of the optimized loop body. Design space exploration
on the FPGA proceeds by varying the number of PEs in the
system. Over four benchmark kernels, our system achieves
3 to 6 relative to soft-core C performance.

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