Par Lab Seminar: Source Snooping Cache Coherence Protocols

10/29/2009 11:00 am
10/29/2009 12:30 pm

Jim Goodman of the University of Auckland will speak on Thursday, October 29 at 11am in 430 Soda Hall (the Woz).

The gap between point-to-point network speeds and buses has grown dramatically in the last few years, leaving the dominant, bus-based snoopy cache coherence methods disadvantaged. Directory-based schemes use point-to-point networks and scale to large numbers of processors, but generally require at least three hops for most cache misses, making them slow for small- or medium-sized systems. Point-to-point networks can be used to broadcast, but the global ordering and synchronization provided by a bus are missing. Intel recently introduced a new cache coherence protocol as part of the QuickPath Interface (QPI), replacing the Front Side Bus (FSB). QPI includes the first example of a "source snooping" protocol to be introduced into a commercial product.

We will discuss source snooping protocols, showing how they can combine both the scalability of directories with the two-hop access delay of snooping caches. We will describe some of the challenges and trade-offs by means of two examples: QPI and MESIF, an ancestral protocol developed in 2001.

Jim Goodman's research is focused on computer architecture: the hardware/software interface. His interests involve high-performance memory systems, particularly for parallel systems, and currently are primarily focused on support for transactional memory, the programming model that dramatically simplifies programming for parallel computers. Hardware-only approaches provide high performance, but limit the size of transactions. Software-only approaches are highly flexible, but suffer serious performance penalties. He is currently developing hybrid approaches that can achieve nearly the performance of hardware but with the flexibility of software.